INSRC=INSRC_0, SSTOP=SSTOP_0, SSTART=SSTART_0
Shifter Configuration N Register
| SSTART | Shifter Start bit 0 (SSTART_0): Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 1 (SSTART_1): Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 2 (SSTART_2): Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 3 (SSTART_3): Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 |
| SSTOP | Shifter Stop bit 0 (SSTOP_0): Stop bit disabled for transmitter/receiver/match store 2 (SSTOP_2): Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 3 (SSTOP_3): Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 |
| INSRC | Input Source 0 (INSRC_0): Pin 1 (INSRC_1): Shifter N+1 Output |
| PWIDTH | Parallel Width |